1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly, to a semiconductor memory device such as an electrically programmable read only memory (EPROM) provided with a data programming circuit for supplying a programming current to memory cells.
2. Description of the Related Art
In general, in an EPROM or other semiconductor memory device, in the program mode, predetermined data is programmed from a data programming circuit to a selected memory cell by storing, or not storing, electric charges in the floating gate of the cell transistor constituting the selected memory cell. On the other hand, in the read mode, the data programmed in the cell transistor is read out by sensing whether or not such electric charges are stored in the floating gate of the cell transistor constituting the selected memory cell.
That is, when programming data "0" in a selected cell transistor of the memory cell array, a programming current is supplied from a programming power source (having a programming potential V.sub.pp) to the selected cell transistor through the data programming circuit, whereupon electrons are accumulated in the floating gate of the selected cell transistor. On the other hand, when programming data "1" in a selected cell transistor of the memory cell array, no programming current is supplied from the programming power source to the selected cell transistor and, therefore, electrons are not accumulated in the floating gate of the cell transistor.
In the above-mentioned conventional data programming circuit, however, in order to reduce the power consumption of the data programming circuit during the read mode, a complementary metal oxide semiconductor (CMOS) type inverter constituted by a P channel transistor and an N channel transistor is normally used as an inverter in the high potential circuit. When such a CMOS type inverter circuit is used, and the potential input to the inverter circuit is high level, the high level input potential is pulled up from V.sub.cc (for example, 5 V) to V.sub.pp (for example, 12.5 V) for stable operation of the inverter circuit. For this purpose, a feedback circuit which feeds back the potential of the output side of the inverter circuit to a pullup transistor is required. With the wiring for the feedback circuit, the wiring pattern of the data programming circuit becomes complicated. Usually, a large number of such wiring patterns are present on a chip, thus making it difficult to realize a small size of the integrated circuit as a whole. This has proven to be a problem.
Further, in general, the programming current during a program mode is determined by the I-V characteristic of the selected cell transistor (current and voltage characteristic between the drain and source of the selected cell transistor) and the load characteristics of the data programming circuit.
Therefore, looking at the I-V characteristic of the cell transistor, while the potential applied between the drain and source of the cell transistor is low, the predetermined current flows through the channel formed between the drain and source. In the program mode (for example, when programming data "0"), however, when a predetermined high potential (for example, 7.5 V) is applied to the drain of the cell transistor from the above data programming circuit, a so-called pinchoff phenomenon occurs and the channel near the drain disappears. An electric field having a high potential is caused there. The electrons, which are given a high energy in the electric field, cause so-called avalanche breakdown and the I-V characteristc of the cell transistor rapidly rises (the current rapidly increases). This large amount of hot electrons caused here is attracted to the floating gate due to the high potential (for example, 12.5 V) applied to the control gate of the cell transistor and is accumulated there. The value of the programming current supplied to the selected cell transistor from the above data programming circuit is determined by the intersection of the characteristic curve indicating the IV characteristic of the cell transistor and the characteristic curve indicating the load characteristics of the above data programming circuit.
However, the I-V characteristics of cell transistors, in particular the above rising portion, differ considerably depending on the gate length (distance between source and drain) of the cell transistors. When the gate length is short, the drain-source potential which initiates the avalanche breakdown falls. On the other hand, when the gate length is long, the drain-source potential which initiates the avalanche breakdown rises. In particular, along with the recent trend toward larger capacity memories, the cell transistors have been made finer in size and their gate lengths have become shorter, thereby resulting in further conspicuous variation in I-V characteristics. This in turn has led to a greater variation in the value of the programming current determined by the intersection of the above two characteristic curves and has resulted in the problem of an inability to ensure a stable programming operation.